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TDA7313 digital controlled stereo audio processor with loudness advance data input multiplexer: - 3 stereo inputs - selectable input gain for optimal adaption to different sources input and output for external equalizer or noise reduction sys- tem loudness function volume control in 1.25db steps treble and bass control four speaker attenuators: - 4 independent speakers control in 1.25db steps for balance and fader facilities - independent mute function all functions programmable via se- rial i 2 c bus description the TDA7313 is a volume, tone (bass and treble) balance (left/right) and fader (front/rear) processor for quality audio applications in car radio and hi-fi systems. selectable input gain and external loudness function are provided. control is accomplished by serial i 2 c bus microprocessor interface. the ac signal setting is obtained by resistor networks and switches combined with operational amplifiers. thanks to the used bipolar/cmos tecnology, low distortion, low noise and low dc stepping are obtained. this is advanced information on a new product now in development or undergoing evaluation. details are subject to change without notice. february 1994 dip28 so28 ordering numbers: TDA7313 TDA7313d pin connection (top view) 1/14
thermal data symbol description so28 dip28 unit r th j-pins thermal resistance junction-pins max 85 65 c/w quick reference data symbol parameter min. typ. max. unit v s supply voltage 6 9 10 v v cl max. input signal handling 2 vrms thd total harmonic distortion v = 1vrms f = 1khz 0.01 0.1 % s/n signal to noise ratio 106 db s c channel separation f = 1khz 103 db volume control 1.25db step -78.75 0 db bass and treble control 2db step -14 +14 db fader and balance control 1.25db step -38.75 0 db input gain 3.75db step 0 11.25 db mute attenuation 100 db absolute maximum ratings symbol parameter value unit v s operating supply voltage 10.2 v t amb operating ambient temperature -40 to 85 c t stg storage temperature range -55 to +150 c test circuit TDA7313 2/14
block diagram TDA7313 3/14
electrical characteristics (refer to the test circuit t amb =25 c, v s = 9v, r l = 10k w , r g = 600 w , all controls flat (g = 0), f = 1khz unless otherwise specified) symbol parameter test condition min. typ. max. unit supply v s supply voltage 6 9 10 v i s supply current 8 11 ma svr ripple rejection 60 80 db input selectors r ii input resistance input 1, 2, 3 35 50 70 k w v cl clipping level 2 2.5 vrms s in input separation (2) 80 100 db r l output load resistance pin 7, 17 2 k w g inmin min. input gain -1 0 1 db g inmax max. input gain 11.25 db g step step resolution 3.75 db e in input noise g = 11.25db 2 m v v dc dc steps adjacent gain steps 4 20 mv g = 18.75 to mute 4 mv volume control r iv input resistance 20 33 50 k w c range control range 70 75 80 db a vmin min. attenuation -1 0 1 db a vmax max. attenuation 70 75 80 db a step step resolution 0.5 1.25 1.75 db e a attenuation set error av = 0 to -20db av = -20 to -60db -1.25 -3 0 1.25 2 db db e t tracking error 2db v dc dc steps adjacent attenuation steps from 0db to av max 0 0.5 3 7.5 mv mv speaker attenuators c range control range 35 37.5 40 db s step step resolution 0.5 1.25 1.75 db e a attenuation set error 1.5 db a mute output mute attenuation 80 100 db v dc dc steps adjacent att. steps from 0 to mute 0 1 3 10 mv mv bass control (1) gb control range max. boost/cut +12 +14 +16 db b step step resolution 1 2 3 db r b internal feedback resistance 34 44 58 k w treble control (1) gt control range max. boost/cut +13 +14 +15 db t step step resolution 1 2 3 db TDA7313 4/14
electrical characteristics (continued) symbol parameter test condition min. typ. max. unit audio outputs v ocl clipping level d = 0.3% 2 2.5 vrms r l output load resistance 2 k w c l output load capacitance 10 nf r out output resistance 30 75 120 w v out dc voltage level 4.2 4.5 4.8 v general e no output noise bw = 20-20khz, flat output muted all gains = 0db 2.5 515 m v m v a curve all gains = 0db 3 m v s/n signal to noise ratio all gains = 0db; v o = 1vrms 106 db d distortion a v =0,v in = 1vrms a v = -20db v in = 1vrms v in = 0.3vrms 0.01 0.09 0.04 0.1 0.3 % % % sc channel separation left/right 80 103 db total tracking error a v = 0 to -20db -20 to -60 db 0 0 1 2 db db bus inputs v il input low voltage 1v v ih input high voltage 3 v i in input current -5 +5 m a v o output voltage sda acknowledge i o = 1.6ma 0.4 v notes: (1) bass and treble response see attached diagram (fig.16). the center frequency and quality of the resonance behaviour can be choosen by the external circuitry. a standard first order bass response can be realized by a standard feedback network (2) the selected input is grounded thru the 2.2 m f capacitor. figure 2: loudness vs. frequency (c loud = 100nf) vs. volume attenuation figure 1: loudness vs. volume attenuation TDA7313 5/14
figure 6: distortion & noise vs. frequency figure 7: distortion & noise vs. frequency figure 8: distortion vs. load resistance figure 4: noise vs. volume/gain settings figure 5: signal to noise ratio vs. volume setting figure 3: loudness vs. external capacitors TDA7313 6/14
figure 12: output clipping level vs. supply voltage figure 14: supply current vs. temperature figure 13: quiescent current vs. supply voltage figure 10: input separation (l1 l2, l3, l4) vs. frequency figure 9: channel separation (l r) vs. frequency figure 11: supply voltage rejection vs. frequency TDA7313 7/14
i 2 c bus interface data transmission from microprocessor to the TDA7313 and viceversa takes place thru the 2 wires i 2 c bus interface, consisting of the two lines sda and scl (pull-up resistors to positive supply voltage must be connected). data validity as shown in fig. 17, the data on the sda line must be stable during the high period of the clock. the high and low state of the data line can only change when the clock signal on the scl line is low. start and stop conditions as shown in fig.18 a start condition is a high to low transition of the sda line while scl is high. the stop condition is a low to high tran- sition of the sda line while scl is high. byte format every byte transferred on the sda line must con- tain 8 bits. each byte must be followed by an ac- knowledge bit. the msb is transferred first. acknowledge the master ( m p) puts a resistive high level on the sda line during the acknowledge clock pulse (see fig. 19). the peripheral (audioprocessor) that ac- knowledges has to pull-down (low) the sda line during the acknowledge clock pulse, so that the sda line is stable low during this clock pulse. the audioprocessor which has been addressed has to generate an acknowledge after the recep- tion of each byte, otherwise the sda line remains at the high level during the ninth clock pulse time. in this case the master transmitter can gen- erate the stop information in order to abort the transfer. transmission without acknowledge avoiding to detect the acknowledge of the audio- processor, the m p can use a simplier transmis- sion: simply it waits one clock without checking the slave acknowledging, and sends the new data. this approach of course is less protected from misworking and decreases the noise immunity. figure 17: data validity on the i 2 cbus figure 16: typical tone response (with the ext. components indicated in the test circuit) figure 15: bass resistance vs. temperature TDA7313 8/14
software specification interface protocol the interface protocol comprises: a start condition (s) a chip address byte, containing the TDA7313 address (the 8th bit of the byte must be 0). the TDA7313 must always acknowledge at the end of each transmitted byte. a sequence of data (n-bytes + acknowledge) a stop condition (p) TDA7313 address msb first byte lsb msb lsb msb lsb s10001000 ack data ack data ack p data transferred (n-bytes + acknowledge) ack = acknowledge s = start p = stop max clock speed 100kbits/s software specification chip address 1 msb 0001000 lsb data bytes msb lsb function 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 1 b2 0 1 0 1 0 1 1 b1 b1 b1 b1 b1 g1 0 1 b0 b0 b0 b0 b0 g0 c3 c3 a2 a2 a2 a2 a2 s2 c2 c2 a1 a1 a1 a1 a1 s1 c1 c1 a0 a0 a0 a0 a0 s0 c0 c0 volume control speaker att lr speaker att rr speaker att lf speaker att rf audio switch bass control treble control ax = 1.25db steps; bx = 10db steps; cx = 2db steps; gx = 3.75db steps figure 18: timing diagram of i 2 cbus figure 19: acknowledge on the i 2 cbus TDA7313 9/14
software specification (continued) data bytes (detailed description) volume msb lsb function 0 0 b2 b1 b0 a2 a1 a0 volume 1.25db steps 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 -1.25 -2.5 -3.75 -5 -6.25 -7.5 -8.75 0 0 b2 b1 b0 a2 a1 a0 volume 10db steps 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 -10 -20 -30 -40 -50 -60 -70 for example a volume of -45db is given by: 00100100 speaker attenuators msb lsb function 1 1 1 1 0 0 1 1 0 1 0 1 b1 b1 b1 b1 b0 b0 b0 b0 a2 a2 a2 a2 a1 a1 a1 a1 a0 a0 a0 a0 speaker lf speaker rf speaker lr speaker rr 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 -1.25 -2.5 -3.75 -5 -6.25 -7.5 -8.75 0 0 1 1 0 1 0 1 0 -10 -20 -30 11111 mute for example attenuation of 25db on speaker rf is given by: 10110100 TDA7313 10/14
audio switch msb lsb function 0 1 0 g1 g0 s2 s1 s0 audio switch 0 1 0 0 1 1 0 1 0 1 stereo 1 stereo 2 stereo 3 stereo 4 (*) loudness on loudness off 0 0 1 1 0 1 0 1 +11.25db +7.5db +3.75db 0db for example to select the stereo 2 input with a gain of +7.5db loudness on the 8bit string is: 01001001 (*) stereo 4 is connected internally, but not available on pins. bass and treble 0 0 1 1 1 1 0 1 c3 c3 c2 c2 c1 c1 c0 c0 bass treble 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 -14 -12 -10 -8 -6 -4 -2 0 0 2 4 6 8 10 12 14 c3 = sign for example bass at -10db is obtained by the following 8 bit string: 01100010 purchase of i 2 c components of sgs-thomson microelectronics, conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specifications as defined by philips. TDA7313 11/14
so28 package mechanical data dim. mm inch min. typ. max. min. typ. max. a 2.65 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 c 0.5 0.020 c1 45 (typ.) d 17.7 18.1 0.697 0.713 e 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 f 7.4 7.6 0.291 0.299 l 0.4 1.27 0.016 0.050 s8 (max.) TDA7313 12/14
dip28 package mechanical data dim. mm inch min. typ. max. min. typ. max. a1 0.63 0.025 b 0.45 0.018 b1 0.23 0.31 0.009 0.012 b2 1.27 0.050 d 37.34 1.470 e 15.2 16.68 0.598 0.657 e 2.54 0.100 e3 33.02 1.300 f 14.1 0.555 i 4.445 0.175 l 3.3 0.130 TDA7313 13/14
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications men- tioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without ex- press written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved sgs-thomson microelectronics group of companies australia - brazil - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thaliand - united kingdom - u.s.a. TDA7313 14/14

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